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1 pin description rev. 0.6, oct. 04, 2001 p/n: pm0767 features ? 128kx 8 organization ? single +5v power supply ? +12v programming voltage ? fast access time:90/100/120/150 ns ? totally static operation ? completely ttl compatible ? operating current:30ma ? standby current: 100ua ? 50 minimum erase/program cycles ? chip erase time: 1 (typ.) ? chip program time: 6.25 (typ.) ? typical fast programming cycle duration 10us/byte ? package type: - 32 pin plastic dip - 32 pin plcc - 32 pin tsop - 32 pin sop general description the mx26c1000b is a 5v only, 1m-bit, mtp eprom tm (multiple time programmable read only memory). it is organized as 128k words by 8 bits per word, operates from a single + 5 volt supply, has a static standby mode, and features fast single address location programming. all programming signals are ttl levels, requiring a single pulse. it is design to be programmed and erased by an eprom programmer or on-board. the mx26c1000b supports a intelligent fast programming algorithm which can result in programming time of less than one minute. this mtp eprom tm is packaged in industry standard 32 pin dual-in-line packages, 32 lead plcc, 32 lead sop and 32 lead tsop packages. pin configurations 32 pdip/sop 32 plcc symbol pin name a0~a16 address input q0~q7 data input/output ce chip enable input oe output enable input we write enable input vpp program supply voltage nc no internal connection vcc power supply pin (+5v) gnd ground pin mx26c1000b 1m-bit [128k x 8] cmos multiple-time-programmable-eprom advance information mx26c1000b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vpp a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc we nc a14 a13 a8 a9 a11 oe a10 ce q7 q6 q5 q4 q3 1 4 5 9 13 14 17 20 21 25 29 32 30 a14 a13 a8 a9 a11 oe a10 ce q7 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd q3 q4 q5 q6 a12 a15 a16 vpp vcc we nc mx26c1000b 32 tsop a11 a9 a8 a13 a14 nc we vcc vpp a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe a10 ce q7 q6 q5 q4 q3 gnd q2 q1 q0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 mx26c1000b
2 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register mx26c1000b flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q7 a0-a16 ce oe we
3 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b functional description when the mx26c1000b is delivered, or it is erased, the chip has all 1000k bits in the "one", or high state. "zeros" are loaded into the mx26c1000b through the procedure of programming. erase algorithm the mx26c1000b do not required preprogramming before an erase operation. the erase algorithm is a close loop flow to simultaneously erase all bits in the entire array. erase operation starts with the initial erase operation. erase verification begins at address 0000h by reading data ffh from each byte. if any byte fails to erase. the entire chip is reerased. to a maximum for 30 pulse counts of 100ms duration for each pulse. the maximum cumulative erase time is 3s. however. the device is usually erased in no more than 3 pulses. erase verification time can be reduced by storing the address of the last byte that failed. following the next erase operation verification may start at the stored address location. jedec standard erase algorithm can also be used. but erase time will increase by performing the unnecessary preprogramming. program algorithm the device is programmed byte by byte. a maximum of 25 pulses. each of 10us duration is allowed for each byte being programmed. the byte may be programmed sequentially or by random. after each program pulse, a program verify is done to determine if the byte has been successfully programmed. programming then proceeds to the next desired byte location. jedec standard program algorithms can be used. reset the reset command initializes the mtp eprom tm device to the read mode. in addition, it also provides the user with a safe method to abort any device operation (including program or erase). the reset command must be written two consecutive times after the set-up program command (40h). this will safely abort any previous operation and initialize the device to the read mode. the set-up program command (40h) is the only command that requires a two sequence reset cycle. the first reset command is interpreted as program data. how ever, ffh data is considered null data during programming operations (memory cells are only programmed from logica "1" to "0". the second reset command safely aborts the programming operation and resets the device to the read mode. this detailed information is for your reference. it may prove esier to always issue the reset command two consecutive times. this eliminates the need to determine if you are in the set-up program state or not. set-up program/program a three-step sequence of commands is required to perform a complete program operation: set up program- program-program verify. the device is bulk erased and byte by byte programming. the command 40h is written to the command register to initiate set up program operation. address and data to be programmed into the byte are provided on the second we pulse. addresses are latched on the falling edge of the we pulse, data are latched on the rising edge of the we pulse. program operation begins on the rising edge of the second we pulse, and terminate of the next rising edge of the we pulse. refer to ac characteristics and waveforms for specific timing parameters. command register when high voltage is applied to v pp the command register is enabled. read, write, standby, output disable modes are available. the read, erase, erase verify, program, program verify and device id are accessed via the command register. standard microprocessor write timings are used to input a command to the register. this register serves as the input to an internal state machine which controls the operation mode of the device. an internal latch is used for write cycles, addresses and data for programming and erase operations. no integrated stop timer for erase leading industry flash technology requires a stop timer built into the flash chip to prevent the memory cells from going into depletion due to over erase. the 1 mbit mtp
4 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b eprom tm is built on an innovative cell concept in which over erasing the memory cell is impossible. data write protection the design of the device protects against accidental erasure or programming. the internal state machine is automatically reset to the read mode on power-up. using control register architecture, alteration of memory can only occur after completion of proper command sequences. the command register is only active when v pp is at high voltage. when v pp = v ppl , the device defaults to the read mode. robust design features prevent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. to avoid initiation of write cycle during v cc power-up, a write cycle is locked out for v cc less than 4v. the two- command program and erase write sequence to the command register provide additional software protection against spurious data changes. program verify mode verification should be performed on the programmed bits to determine that they were correctly programmed. verification should be performed with oe and ce, at vil, we at vih, and vpp at its programming voltage. erase verify mode verification should be performed on the erased chip to determine that the whole chip(all bits) was correctly erased. verification should be performed with oe and ce at vil, we at vih, and vcc = 5v, vpp = 12.5v auto identify mode the auto identify mode allows the reading out of a binary code from mtp eprom that will identify its manufacturer and device type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional in the 25 c 5 c ambient temperature range that is required when programming the mx26c1000b. to activate this mode, the programming equipment must force 12.0 0.5 v on address line a9 of the device. two identifier bytes may then be sequenced from the device outputs by toggling address line a0 from vil to vih. all other address lines must be held at vil during auto identify mode. byte 0 ( a0 = vil) represents the manufacturer code, and byte 1 (a0 = vih), the device identifier code. for the mx26c1000b, these two identifier bytes are given in the mode select table. all identifiers for manufacturer and device codes will possess odd parity, with the msb (dq7) defined as the parity bit. read mode the mx26c1000b has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that addresses are stable, address access time (tacc) is equal to the delay from ce to output (tce). data is available at the outputs toe after the falling edge of oe, assuming that ce has been low and addresses have been stable for at least tacc - toe. standby mode the mx26c1000b has a cmos standby mode which reduces the maximum vcc current to 100 ua. it is placed in cmos standby when ce is at vcc 0.3 v. the mx26c1000b also has a ttl-standby mode which reduces the maximum vcc current to 1.5 ma. it is placed in ttl-standby when ce is at vih. when in standby mode, the outputs are in a high-impedance state, independent of the oe input. system considerations during the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of chip enable. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. at a minimum, a 0.1 uf ceramic capacitor (high frequency, low inherent inductance) should be used on each device between vcc and gnd to minimize transient effects. in addition, to overcome the voltage drop caused by the inductive
5 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b table 1: bus operations mode vpp(1) a0 a9 ce oe we q0~q7 read vppl a0 a9 vil vil vih data out read-only output disable vppl x x vil vih vih tri-state mode s tandby vppl x x vih x x tri-state manufacturer identification vppl vil vid(2) vil vil vih data=c2h device identification vppl vih vid(2) vil vil vih data=cfh read vpph a0 a9 vil vil vih data out(3) command output disable vpph x x vil vih vih tri-state mode standby(4) vpph x x(5) vih x x tri-state program vpph a0 a9 vil vih vil data inb note: 1. refer to dc characteristics. when vpp=vppl memory contents can be read but not written or erased. 2. vid is the intelligent identifier high voltage. refer to dc characteristics. 3. read operations with vpp=vpph may access array data or the intelligent identifier codes. 4. with vpp at high voltage the standby current equals icc+ipp(standby). 5. refer to table 2 for vaild data-in during a write operation. 6. x can be vil or vih. effects of the printed circuit board traces on eprom arrays, a 4.7 uf bulk electrolytic capacitor should be used between vcc and gnd for each of the eight devices. the location of the capacitor should be close to where the power supply is connected to the array. output disable output is disabled when oe is at logre high. when in output disabled all circuitry is enabled. except the output pins are in a high impedance state(tri-atate).
6 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b command mode the 1 mbit mtp eprom tm is in command mode when high voltage v pph is applied to the v pp pin. in this state the available functions are read, program, program verify, erase and erase verify. reset are selected by writing commands to the input register. data from the register are input to the state machine. the output from the state machine determines the function of the device. the command register serves as a latch to store data for executing commands. it does not occupy address- able memory location. standard microprocessor write timing is used. table 2 defines the register commands. the command register is written by bringing we to a logic-low level (v il ), while ce is low. addresses are latched on the falling edge of we, while data is latched on the rising edge of the we pulse. standby and output disable functions are the same as in read mode, controlled by ce and oe. if the device is deselected during erasure, programming, or erase/ program verification, the device draws active current until the operations terminate. read command to read memory content, write 00h into the command register while high voltage is applied to v pp pin (v pp = v pph ). microprocessor read cycle retrieves the data . the device remains enable for read until the data in the command register are altered. the device is default in read mode when power up. this is to ensure no accidental alteration of the memory occurs during power transition. refer to ac read characteristics and waveforms for specific timing parameters. set up erase/erase preprogram operation is not required prior to the erase operation. a sequence of commands is required to perform a complete erase operation: set up erase, erase, and erase verify. high voltage is applied to the v pp pin (v pp =v pph ). the command 20h is written to the command register to initiate the set-up erase mode. erase operation the same command, 20h, is again written to the command register. this second command starts bulk erase operation. the two-step command prevents accidental alteration to memory array. erase operation starts with the rising edge of the we pulse and terminates with the rising edge of the next we pulse, which in this case is the erase verify command. erase verify each erase operation is followed by an erase verify. the command a0h is written into the command register. the address of the bytes to be verified is supplied with the command. the address is latched on the falling edge of the we pulse. a reading ffh is returned to confirm all bits in the byte are erased. this sequence of set up erase- erase continues for each address until ffh is returned. this indicates the entire memory array is erased and completes the operation. erase verify operation starts at address 0000h and ends at the last address. maximum erase pulse duration for the 1mbit mtp eprom tm is 100ms with a maximum 30 pulses. refer to ac characteristics and waveforms for specific timing parameters.
7 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b programming algorithm flow chart start programming programming completed apply v pph write read cmd increment address apply v ppl programming error apply v ppl plscnt=0 write set-up program cmd yes yes no no no write program cmd(a/d) time out 10us time out 6us read data from device write program verify cmd verify data ? inc plsnt=25 ? yes last address ?
8 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b erase algorithm flow chart start erasure erasure completed apply v pph write read cmd increment address apply v ppl erasure error apply v ppl address=00h plscnt=0 write set-up erase and erase cmd yes yes no no no time out 100ms time out 6us read data from device write erase verify cmd data=ffh ? inc plsnt=30 ? yes last address ?
9 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b switching test circuits switching test waveforms device under test diodes = in3064 or equivalent cl = 100 pf including jig capacitance 6.2k ohm 1.8k ohm +5v cl 2.0v 0.8v test points input 2.0v 0.8v output ac testing: ac driving levels are 2.4v/0.4v for commercial grade. input pulse rise and fall times are equal to or less than 10ns. ac driving levels
10 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b notice: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. notice: specifications contained within the following tables are subject to change. absolute maximum ratings rating value ambient operating temperature -40 o c to 85 o c storage temperature -65 o c to 125 o c applied input voltage -0.5v to 7.0v applied output voltage -0.5v to vcc + 0.5v vcc to ground potential -0.5v to 7.0v a9 & vpp -0.5v to 13.5v capacitance ta = 25 o c, f = 1.0 mhz (sampled only) symbol parameter typ. max. unit conditions cin input capacitance 8 12 pf vin = 0v cout output capacitance 8 12 pf vout = 0v cvpp vpp capacitance 18 25 pf vpp = 0v mx26c1000b -90 -100 -120 -150 operating temperature industrial -40 c to 85 c -40 c to 85 c -40 c to 85 c -40 c to 85 c vcc power supply 5v 10% 5v 10% 5v 10% 5v 10% dc/ac operating condition for read operation dc characteristics ta = -45 c ~ 85 c, vcc=5v 10% symbol parameter min. max. unit conditions vil input low voltage -0.3 0.8 v vih input high voltage 2.0 vcc + 0.5 v vol output low voltage 0.4 v iol = 2.1ma, vcc=vcc min voh output high voltage 2.4 v ioh = -0.4ma icc1 vcc active current 30 ma ce = vil, oe=vih, f=5mhz isb vcc standby current (cmos) 100 ua ce=vcc+0.2v, vcc=vcc max isb vcc standby current (ttl) 1.5 ma ce=vih, vcc=vcc max ipp vpp read current 100 ua ce = oe = vil, vpp = 5.5v ipp2 vpp supply current 30 ma ce=we=vil, oe=vih (program/erase) ili input leakage current -10 10 ua vin = 0 to 5.5v ilo output leakage current -10 10 ua vout = 0 to 5.5v vcc1 fast programming supply voltage 6.0 6.5 v vpp1 fast programming voltage 12.5 13.0 v
11 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b ac raed characteristics over operating range with vpp=vcc symbol parameter 90 100 120 150 unit jeded std min max min max min max min max tavav trc read cycle time 90 100 120 150 ns telqv tce ce access time 0 90 0 100 0 120 0 150 ns tavqv tacc address access time 0 90 0 100 0 120 0 150 ns tglqv toe oe access time 0 40 0 45 0 50 0 65 ns telqx tlz ce to output in low z(note 1) 0 0 0 0 ns tehqz tdf chip disable to output in high z(note 2) 0 30 0 35 0 35 0 50 ns tglqx tolz oe to output in low z (note 1) 0 0 0 0 ns tghqz tdf output disable to output in high z 0 30 0 35 0 35 0 50 ns (note 1) taxqx toh output hold from address, ce or oe, 0 0 0 0 ns change twhgl twhgl write recovery time before read 6 6 6 6 us tvcs tvcs vcc setup time to valid read (note 2) 50 50 50 50 us note: 1. sampled: not 100% tested. 2. guaranteed by design. not tested.
12 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b ac characteristics - write/erase/program operations symbol parameter 90 100 120 150 unit jeded std min max min max min max min max tavav twc write cycle time (note 3) 90 100 120 150 ns tavwl tas address setup time 0 0 0 0 ns twlax tah address hold time 40 40 40 40 ns tdvwh tds data setup time 40 40 40 40 ns twhdx tdh data hold time 10 10 10 10 ns twhgl twr write recovery time before read 6 6 6 6 us tghwl tdes read recovery time before write 0 0 0 0 us telwl tcs ce setup time before write 0 0 0 0 ns twheh tch ce hold time 0 0 0 0 ns twlwh twp write pulse width 50 50 50 50 ns twhwl twph write pulse width high 20 20 20 20 ns twhwh1 duration of programming operation 10 10 10 10 us (note2) twhwh2 duration of erase operation(note2) 100 100 100 100 ms tvpel vpp setup time to chip enable low 1 1 1 1 us (note 3) tvcs vcc setup time to chip enable low 50 50 50 50 us (note 3) tvppr vpp rise time (note 3) 90% vpph 500 500 500 500 ns tvppf vpp fall time (note 3) 10% vpph 500 500 500 500 ns note: 1. read timing characteristics during read/write operations are the same as during read-only operations. refer to ac characteristics for read only operations. 2. maximum pulse widths not required because the on-chip program/erase circuitry will terminate the pulse widths internally on the device. 3. not 100% tested.
13 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b table 2: command definitions command bus first bus cycle second bus cycle cycles. req operation address 1 data 2 operation address 1 data 2 read memory 1 write x 00h setup erase/erase 2 write x 20h write x 20h erase verify 2 write ea a0h read x evd setup program/program 2 write x 40h write pa pd program verify 2 write x c0h read x pvd reset 2 write x ffh write x ffh 1 ea=erase address: address of memory location to be read during erase verify. pa=program address: address of memory location to be programmed. address are latched on the falling edge of the we pulse. 2 evd=erase verify data: data read from location ea during erase verify. pd=program data: data to be programmed at location pa. data is latched on the rising edge of we. pvd=program verify data: data read from location pa during program verify. pa is latched on the program command.
14 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b ac waveforms for read operations address ce oe we data vcc taxqx(toh) tghqz(tdf) tehqz(tdf) tavav(trc) tglqv(toe) telqx(tlz) tglqx(tolz) telqv(tce) twhgl tvcs tavqv(tacc) high z 5.0v 0v power-up standby device and address selection outputs enabled data valid standby power-up high z addresses stable output valid
15 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b ac waveforms for erase operations addresses ce oe we data vcc tavav(twc) tavwl(tas) telwl(tcs) twheh(tch) tghwl(tdes) twlwh(twp) twhwl(twph) tvcs tvpel tdvwh(tds) twhdx(tdh) tavav(trc) tehqz(tdf) tghqz(tdf) tglqx(tolz) tglqv(toe) taxqx(toh) telqx(tlz) telqv(tce) tavwl(tas) twhwh1 twhgl twlax(tah) power-up standby setup program program command latch program address and data programming verify command programming verification standby power-down data in=40h data in=pd 5v 0v vpp vpph vppl data in=c0h valid data out
16 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b ac waveforms for programming operations addresses ce oe we data vcc tavav(twc) tavwl(tas) telwl(tcs) twheh(tch) tghwl(tdes) twlwh(twp) twhwl(twph) tvcs tvpel tdvwh(tds) twhdx(tdh) tavav(trc) tehqz(tdf) tghqz(tdf) tglqx(tolz) tglqv(toe) taxqx(toh) telqx(tlz) telqv(tce) tavwl(tas) twhwh1 twhgl twlax(tah) power-up standby setup program program command latch address and data programming verify command programming verification standby power-down data in=20h data in=20h 5v 0v vpp vpph vppl data in=c0h valid data out
17 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b ordering information plastic package part no. access time(ns) operating standby operating package current max.(ma) current max.(ua) temperature mx26c1000bpc-90 90 30 100 0 c to 70 c 32 pin dip mx26c1000bqc-90 90 30 100 0 c to 70 c 32 pin plcc mx26c1000bmc-90 90 30 100 0 c to 70 c 32 pin sop mx26c1000btc-90 90 30 100 0 c to 70 c 32 pin tsop mx26c1000bpc-10 100 30 100 0 c to 70 c 32 pin dip mx26c1000bqc-10 100 30 100 0 c to 70 c 32 pin plcc mx26c1000bmc-10 100 30 100 0 c to 70 c 32 pin sop MX26C1000BTC-10 100 30 100 0 c to 70 c 32 pin tsop mx26c1000bpc-12 120 30 100 0 c to 70 c 32 pin dip mx26c1000bqc-12 120 30 100 0 c to 70 c 32 pin plcc mx26c1000bmc-12 120 30 100 0 c to 70 c 32 pin sop mx26c1000btc-12 120 30 100 0 c to 70 c 32 pin tsop mx26c1000bpc-15 150 30 100 0 c to 70 c 32 pin dip mx26c1000bqc-15 150 30 100 0 c to 70 c 32 pin plcc mx26c1000bmc-15 150 30 100 0 c to 70 c 32 pin sop mx26c1000btc-15 150 30 100 0 c to 70 c 32 pin tsop mx26c1000bpi-90 90 30 100 -40 c to 85 c 32 pin dip mx26c1000bqi-90 90 30 100 -40 c to 85 c 32 pin plcc mx26c1000bmi-90 90 30 100 -40 c to 85 c 32 pin sop mx26c1000bti-90 90 30 100 -40 c to 85 c 32 pin tsop mx26c1000bpi-10 100 30 100 -40 c to 85 c 32 pin dip mx26c1000bqi-10 100 30 100 -40 c to 85 c 32 pin plcc mx26c1000bmi-10 100 30 100 -40 c to 85 c 32 pin sop mx26c1000bti-10 100 30 100 -40 c to 85 c 32 pin tsop mx26c1000bpi-12 120 30 100 -40 c to 85 c 32 pin dip mx26c1000bqi-12 120 30 100 -40 c to 85 c 32 pin plcc mx26c1000bmi-12 120 30 100 -40 c to 85 c 32 pin sop mx26c1000bti-12 120 30 100 -40 c to 85 c 32 pin tsop mx26c1000bpi-15 150 30 100 -40 c to 85 c 32 pin dip mx26c1000bqi-15 150 30 100 -40 c to 85 c 32 pin plcc mx26c1000bmi-15 150 30 100 -40 c to 85 c 32 pin sop mx26c1000bti-15 150 30 100 -40 c to 85 c 32 pin tsop
18 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b package information 32-pin plastic dip(600 mil)
19 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b 32-pin plastic leaded chip carrier (plcc)
20 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b 32-pin plastic tsop
21 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b 32-pin plastic sop (450 mil)
22 rev. 0.6, oct. 04, 2001 p/n: pm0767 mx26c1000b revision history revision no. description page date 0.1 change title from mx26c1000a to mx26c1000b all dec/11/2000 to add erase/program cycle p1 0.2 change device id code from 30h to ceh p5 dec/28/2000 0.3 to added 32sop/tsop types package and access time 150ns p1,11,12,17,18 mar/27/2001 modify device id old ceh-->new cfh p5 modify read id method p4,5,6,13 modify erase/program cycle from 100ns to 50ns p10 modify vcc standby current(ttl) from 1ma to 1.5ma p10 0.4 to added vcc1 & vpp1 to dc characteristics table p10 apr/23/2001 modify package information p18~21 0.5 to added chip erase time / chip program time p1 jul/04/2001 modify package information p18~21 0.6 modify the programming operations timing waveforms p15 oct/04/2001
23 mx26c1000b m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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